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In this paper, we propose a new digital signal processor architecture SPVA (Scalable Parallel VLIW architecture) for Software Defined Radio. The proposed architecture organizes function units into arithmetic units, and other units. The former are organized as SIMD clusters and the latter are organized as control clusters. Advantages of the proposed architecture include exploiting data parallelism through SIMD VLIW clusters, hiding memory latency through static schedule schemes, and exposing delay of branch and memory access to programmers and compilers. The experiments' results on critical benchmarks show that this architecture provides significant computation speedup compared to conventional VLIW DSP.