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A 9-bit Quadrature Direct Digital Synthesizer Implemented in 0.18- \mu{\hbox {m}} SiGe BiCMOS Technology

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4 Author(s)
Xuefeng Yu ; Dept. of Electr. Eng., Auburn Univ., Auburn, AL ; Fa Foster Dai ; J. David Irwin ; Richard C. Jaeger

This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-mum SiGe BiCMOS technology. With a 9-bit pipeline accumulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed with more than 13 500 transistors, the quadrature DDS occupies an active area of 2.3 times 2.5 mm2 and a total die area of 3.0 times 3.0 mm2. The measured spurious-free dynamic range is approximately 26 dBc at a clock frequency 6.2 GHz. At the maximum clock frequency, the power consumption of the DDS is 2.5 W with 3.3- and 4.0-V power supplies for the digital and analog parts, respectively. The DDS thus achieves a power efficiency figure-of-merit of 5.04 GHz/W/phase. The DDS chips were packaged with 48-pin ceramic leadless chip carriers and air cooling was used during the measurement.

Published in:

IEEE Transactions on Microwave Theory and Techniques  (Volume:56 ,  Issue: 5 )