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Due to reduction in device feature size and supply voltage, the sensitivity to radiation-induced transient faults of digital systems dramatically increases. In this paper, we present two approaches to evaluating the susceptibility of sequential circuits to soft errors. The first approach uses the Markov chain theory but can only provide steady-state behavior information. The second approach uses symbolic modeling based on binary decision diagrams/algebraic decision diagrams and circuit unrolling. The soft-error rate (SER) evaluation using this approach is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10-7 FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11 000x faster when compared to HSPICE detailed circuit simulation. The framework can be used for selective gate sizing targeting radiation hardening, leading up to 80% SER reduction when applied to a subset of ISCAS'89 benchmarks.