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Performance Analysis of Cache and Scratchpad Memory in an Embedded High Performance Processor

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2 Author(s)
Dias, W.P. ; Brazilian Aeronaut. Inst. of Technol., Sao Jose dos Campos ; Colonese, E.

The objective of this article is to present a comparative study of an embedded processor performance using architecture with cache or scratchpad memory in relation to an architecture with only external synchronous dynamic random access memory. For this analysis the ADSP-BF533 of analog devices, a high performance processor, was used. The adjusted memory space was configured and analyzed during the process of a small data volume, and great data volume, in three different speeds of the core, and in one same speed of the processor external memory. The scratchpad memory has shown better performance in programs with small data volume; however the cache memory had a better performance for large data allocation.

Published in:

Information Technology: New Generations, 2008. ITNG 2008. Fifth International Conference on

Date of Conference:

7-9 April 2008