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Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

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3 Author(s)
Kim, T. ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon ; Jeong, Y. ; Yang, K.

The low-power/high-speed performance of current-mode logic (CML) D flip-flops based on negative-differential-resistance (NDR) devices is presented. The device count used in the fabricated circuit has been significantly reduced by using the NDR-based D flip-flop topology, leading to enhanced low-power/high-speed performance. The operation of the fabricated NDR-based CML D flip-flop has been confirmed to 36 Gb/s, which is the highest speed among NDR-based differential-mode D flip-flops reported to date. The power consumption of the D flip-flop core circuit was measured to be as low as 20 mW at a power supply voltage of -3.3 V. In addition, a power-delay product of 0.55 pJ has been obtained from the NDR-based CML D flip- flop, which is the lowest value to the authors' knowledge among the previously reported D flip- flops up to operation speeds in the region of 40 Gb/s.

Published in:

Circuits, Devices & Systems, IET  (Volume:2 ,  Issue: 2 )