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This paper presents a new bang-bang phase detector and a new charge-pump frequency detector and their applications in dual-loop phase-locked loops. The regenerative operation of the proposed bang-bang phase detector ensures a fast acquisition of incoming clocks while the charge-pump frequency detector effectively detects the frequency difference between the reference clock and local VCO. The effectiveness of the proposed phase/frequency detectors is assessed by incorporated them in a 2 GHz dual-loop phase-locked loop implemented in UMC- 0.13 mum 1.2V CMOS technology and analyzed using Spectre with BSIM3.3v device models. Simulation results demonstrate that the PLL reaches the lock state in 600 cycles with phase noise of -125 dBc/Hz at 1 MHz frequency offset.