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A delay line with highly linear thermal sensitivity for smart temperature sensor

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3 Author(s)

A highly linear thermal sensitivity delay line for smart temperature sensor is presented. The proposed delay line is a current starved inverter chain. A simple bias current source circuit is incorporated with the delay line to generate a current inversely proportional to temperature based on the transconductance characteristics of a MOS device at the vicinity of the zero temperature coefficient (ZTC) point. Simulation results in a 0.18 mum CMOS technology show that the proposed delay line has a higher linearity within 0.24degC in a wider temperature range from -40degC to 120degC compared with conventional structures.

Published in:

Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on

Date of Conference:

5-8 Aug. 2007