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With shrinking process node sizes, the inherent effect of process variations is playing a larger factor in defining the behavior of a circuit. conventional static timing analysis (STA) using best case/worst case analysis is overly pessimistic, and could be optimistic also in some cases. This has resulted in the promotion of statistical static timing analysis (SSTA) as a method for estimating yield of a circuit in terms of timing activities. Model extraction is a technique that accurately captures the characteristics of interface logic of a design in the form of a timing library model and provides a capacity improvement in timing verification by more than two orders of magnitude. Timing extraction plays an important role in the hierarchical analysis flows by reducing the complexity of timing verification. Current model extraction techniques are not capable generating timing models which can be used for SSTA of the complete chip. In this work, we propose a technique for generating a Statistical (or Variation Aware) Extracted Timing Model (S-ETM) to be used in conjunction with any sensitivity based SSTA engine. We also describe a method for validating S-ETM.