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This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most 8 reference cycles. ASICs in CMOS AMS 0,35 um and UMC 0,13 um have been manufactured and tested. Measurements show competitive results to state-of-the- art mixed signal implementations.