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The analytical MOSFET intrinsic delay introduced in Part I of this paper is used to examine the tradeoffs between key device elements required in order for the performance scaling trend to continue in future high-performance CMOS generations. A scaling scenario based on contacted source/drain gate pitch is presented and used to examine the prospects of MOSFET performance in the future nodes. It is shown that, from 32-nm node onwards, MOSFET performance will counterscale, mainly due to increase in the parasitic gate capacitance as a result of proximity of the gate and source/drain electrodes. As a case study, the dependence of the transistor performance on various device parameters at the 32-nm node is analyzed. Reducing the fringing capacitance is shown to be the most effective approach to meet the required transistor delay.