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To increase the sampling rate of Analog to Digital Converters (ADC), Time-Interleaved ADC (TIADC) is an efficient solution. However, offset mismatch, gain mismatch, and timing errors between time-interleaved channels limit the TIADC performances. This setting presents a new adaptive method for gain and offset mismatch error compensation. The technique proposed is based on adaptive filtering process using DLMS algorithm. Mixed simulations using VHDL - AMS language show spectral performance improvement. A material implementation on FPGA is presented to evaluate the consumed resources.
Date of Conference: 5-8 Aug. 2007