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An RNS-Enhanced Microprocessor Implementation of Public Key Cryptography

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2 Author(s)
Zhining Lim ; Univ. of Adelaide, Adelaide ; Phillips, B.J.

This paper presents a new residue number system implementation of the RSA cryptosystem. The system runs on a low-area, low-power microprocessor that we have extended with hardware support for residue arithmetic. When compared against a baseline implementation that uses non-RNS multi-precision methods, the new RNS implementation executes in 67.7% fewer clock cycles. The hardware support requires 42.7% more gates than the base processor core.

Published in:

Signals, Systems and Computers, 2007. ACSSC 2007. Conference Record of the Forty-First Asilomar Conference on

Date of Conference:

4-7 Nov. 2007