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Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits

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3 Author(s)
Feinstein, D.Y. ; Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX ; Thornton, M.A. ; Miller, D.M.

This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.

Published in:

Design, Automation and Test in Europe, 2008. DATE '08

Date of Conference:

10-14 March 2008