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According to statistics the verification of digital integrated circuits (IC) claims up to 70 % of the design time and effort in the design process. This means that the verification process must be well structured and organized in order to efficiently reach desired verification goals. This paper describes the modelling of an exhaustive formal verification process of a digital IC with Workflow Petri Nets  and the WoPeD (Workflow Petri net Designer) tool , which supports modelling, simulation and analysis of a workflow process. The purpose of this work is to formalize and quantify the verification process such that it could subsequently be structurally and behaviourally analyzed according to the means provided by Petri Nets and, if desired, simulated with a particular scenario. This approach makes it possible to explicitly examine and derive the interaction of different factors which influence a verification process such that their relationships could be quantified. Initial experimental results are presented and advantages and disadvantages of this methodology are discussed.