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A low-cost concurrent error detection technique for processor control logic

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5 Author(s)
Vemu, R. ; Comput. Eng. Res. Center, Univ. of Texas, Austin, TX ; Jas, A. ; Abraham, J.A. ; Patil, S.
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This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transient faults, the technique selects faults which have a high probability of causing damage to the architectural state of the processor and protects the circuit against these faults. Fault detection is achieved through a series of assertions. Each assertion is an implication from inputs to the outputs of a combinational circuit. Fault simulation experiments performed on control logic modules of an industrial processor suggest that high reduction in damage causing faults can be achieved with a low overhead.

Published in:

Design, Automation and Test in Europe, 2008. DATE '08

Date of Conference:

10-14 March 2008

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