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Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip

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4 Author(s)
Moonen, A. ; Univ. of Technol. Eindhoven, Eindhoven ; Bekooij, M. ; van den Berg, R. ; Van Meerbergen, J.

Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor system- on-chip. An external memory that is shared between processors is a bottleneck in current and future systems. Cache misses and a large cache miss penalty contribute to a low processor utilisation. In this paper, we describe a novel cache optimisation technique to reduce instruction and data cache misses for streaming applications. The instruction and data locality are improved by executing a task multiple times before moving to the next task. Furthermore, we introduce a dataflow model that is used to trade-off the number of cache misses against end-to-end latency and memory usage. For our industrial application, which is a Digital Radio Mondiale receiver, the number of cache misses is reduced with a factor 4.2.

Published in:

Design, Automation and Test in Europe, 2008. DATE '08

Date of Conference:

10-14 March 2008

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