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MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices

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2 Author(s)
Paul, S. ; Case Western Reserve Univ., Cleveland ; Bhunia, S.

While the emerging nanoscale devices show promises in terms of integration density and computing power, system design with these devices involve some major challenges, such as bottom-up design approach, effective integration with CMOS and defect tolerance. To address some of these challenges, we propose MBARC, a reconfigurable framework using memory as the primary computing element. The proposed framework leverages on the reported advantages of memory array design with nanodevices, which are compatible to fabrication into dense and regular structures. The main idea is to partition a logic circuit, implement the partitions as multi-input multi-output lookup tables in a memory array, and then use a simple CMOS-based scheduler to evaluate the partitions in topological time-multiplexed manner. Compared to existing reconfigurable nanocomputing models, the proposed memory based computing has three major advantages: 1) it minimizes the requirement of programmable interconnects, thus, saving design cost; 2) it minimizes the number of CMOS interfacing elements (required for level restoration and cascading logic blocks); 3) existing techniques for defect tolerance in memory array can be easily extended to this framework. Simulation results for a set of ISCAS benchmarks show average improvement of 32% in area, 21% in delay and 34% in energy per vector compared to nanoscale FPGA implementation.

Published in:

Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific

Date of Conference:

21-24 March 2008

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