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Symmetry constraint based on mismatch analysis for analog layout in SOI technology

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6 Author(s)
Jiayi Liu ; EDA Lab, Tsinghua Univ., Beijing, 100084 China ; Sheqin Dong ; Xianlong Hong ; Yibo Wang
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The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

Published in:

2008 Asia and South Pacific Design Automation Conference

Date of Conference:

21-24 March 2008