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Experiences of low power design implementation and verification

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2 Author(s)
Shi-Hao Chen ; Global Unichip Corp., Hsinchu ; Jiing-Yuan Lin

In this paper, we present the experiences of some low power solutions that have been successfully implemented in 90 nm/65 nm production tape-outs. We also focus on power gating design, an effective low leakage solution, and present the experiences of power switch planning, optimization, and verification. Dynamic IR drop is an important issue in low power design, which may reduce the logic gate noise margins and result in functional or timing failures. We will present a low cost but effective methodology for dynamic IR drop prevention and fixing.

Published in:

Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific

Date of Conference:

21-24 March 2008