Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
3 Author(s)
Homma, K. ; Fujitsu Labs. Ltd., Kawasaki ; Nitta, I. ; Shibuya, T.

Statistical timing analysis (SSTA) is a method that calculates circuit delay statistically with process parameter variations, die-to-die (D2D) and within-die (WID) variations. In this paper, we model that WID parameter variations are independent for each cell and line in a chip and D2D variations are governed by one variation on a chip. We propose a new method of computing a full chip delay distribution considering both D2D and WID parameter variations. Experimental results show that the proposed method is more accurate than previous methods on actual chip designs.

Published in:

Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific

Date of Conference:

21-24 March 2008