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Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis

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3 Author(s)
Katsumi Homma ; Fujitsu Laboratories Ltd. 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki-shi, 211-8588 Japan ; Izumi Nitta ; Toshiyuki Shibuya

Statistical timing analysis (SSTA) is a method that calculates circuit delay statistically with process parameter variations, die-to-die (D2D) and within-die (WID) variations. In this paper, we model that WID parameter variations are independent for each cell and line in a chip and D2D variations are governed by one variation on a chip. We propose a new method of computing a full chip delay distribution considering both D2D and WID parameter variations. Experimental results show that the proposed method is more accurate than previous methods on actual chip designs.

Published in:

2008 Asia and South Pacific Design Automation Conference

Date of Conference:

21-24 March 2008