By Topic

Constraint-free analog placement with topological symmetry structure

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Qing Dong ; Department of Information and Media Sciences, University of Kitakyushu, Wakamatsu, Fukuoka, 808-0135, Japan ; Shigetoshi Nakatake

In analog circuits, blocks need to be placed symmetrically to satisfy the devices matching. Different from the existing constraint-driven approaches, the proposed topological symmetry structure enables us to generate a symmetrical placement without any constraint. Simulated annealing is utilized as the framework of the optimization, and we propose new move operation to maintain the placement's topological symmetry. By inserting dummy blocks, we present a physical skewed symmetry structure allowing non-symmetry partly, so that to enhance the placement on area and wire length. Besides, we incorporate regularity into the evaluation of placement. Experiments shows that our approach generated topological complete symmetry placements without much compromise on chip area and wire length, compared to the placements with no symmetry.

Published in:

2008 Asia and South Pacific Design Automation Conference

Date of Conference:

21-24 March 2008