Design and implementation of an FPGA-based multi-standard software radio receiver

The aim of this work is to design and implement an FPGA-based multi-standard software radio receiver. WLAN and UMTS are taken as the case study. Xilinx FPGA Virtex- IV is the target platform. Bandpass sampling technique at 840 MHz is used to alias the combined band of WLAN and UMTS. In the channelization process, in contrast to conventional channelizer, polyphase channelizer is employed. The designed prototype filter for WLAN has 50 taps, partitioned into 5 polyphase sub-filters whereas for the UMTS the prototype filter has 2520 taps, partitioned into 210 polyphase sub-filters. In the implementation, serial polyphase structure with parallel MAC is selected. An implementation analysis based on the area requirements for multipliers, adders and registers for different structures is performed. For 16-tap filter, the structures for parallel-multiply and accumulate, DA, Fast FIR, and Frequency domain filtering require 2896 (without adders), 3072, 4064, and 5572 slices, respectively. The DA is found to be suitable for the implementation due to being resource efficient. Polyphase sub-filter is implemented with distributed arithmetic structure and also with Xilinx-DSP48 slices for improved performance.