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Integrated circuit manufacturability in DSM is directly dependent on how well the manufacturing variations are accounted for during the design of circuits. This paper reviews the effect of various process variations in DSM especially systematic and random variations in three process generations 90 nm, 65 nm & 45 nm by doing SPICE simulation and analysis to look at the derating factors depending on the sensitivity to variations. Few individual standard cells are studied as apart of this exercise to see the effect of variation on their delays. Random variations are becoming a significant portion of the overall variations at 45 nm and below. The results suggests the need for selective, location based and variation aware analysis (SLVA) for the designs going forward.