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Summary form only given. Choosing data storage arrays for a microprocessor design is driven by a delicate balance of technology readiness, circuit-level design factors, and system-level performance, power, and scaling implications. Recently, CMOS technologists have warned of the "end of scaling," and cite particular concern for six-transistor SRAM. This is a startling forecast, since easily 50% of microprocessor silicon area is commonly occupied by SRAM caches. A particularly long-standing debate has surrounded one dense, resilient, on-chip storage alternative: embedded DRAM. This tutorial will provide background on eDRAM, and show how its circuit and technology properties translate to metrics used to make decisions at the chip and architecture levels: cache capacity, cache access latency, and cache distance from the CPU.