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Tutorial 4: Robust System Design in Scaled CMOS

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1 Author(s)
Subhasis Mitra ; Stanford Univ., Stanford

Summary form only given. The aim of this paper is to develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems without incurring the high cost of traditional redundancy. An architecture-aware circuit design technique corrects radiation-induced soft errors in latches, flip-flops, and combinational logic at extremely low-cost compared to redundancy techniques. A new design technique, distinct from error detection, predicts failures before they actually create errors in system data and states. Circuit failure prediction is ideal for reliability mechanisms such as transistor aging and early-life failures, and can enable close to best-case design by minimizing traditional worst-case speed guardbands.

Published in:

9th International Symposium on Quality Electronic Design (isqed 2008)

Date of Conference:

17-19 March 2008