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Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies

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1 Author(s)
Kim, C. ; Univ. of Minnesota, Minneapolis

Summary form only given. In order to continue CMOS scaling towards the physical limit, care must be taken to account for each obstacle that is currently impeding our progress. Increased power consumption and faster current transients have deteriorated on-chip power supply integrity. Long term reliability issues such as negative bias temperature instability (NBTI) have become serious problems degrading the performance and yield of high performance systems. This talk will focus on circuit design techniques to deal with power supply noise and aging issues in sub-32nm technologies. First, modeling and design techniques are presented for reliable on-chip power supply delivery. Next, an overview of several reliability mechanisms will be given followed by some recent developments on monitoring techniques to accurately measure and model the circuit aging impact.

Published in:

Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on

Date of Conference:

17-19 March 2008

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