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This paper investigates a bidirectional- and multi-drop-transmission-line interconnect for on-chip high-speed networks that have big impact in chip performances. Point-to-point on-chip transmission line interconnects have been developed and demonstrated widely. The present paper applies transmission line interconnect technologies to multipoint-to-multipoint on-chip communications. We propose the novel transceiver that consists of a single differential-amplifier and serves as both a transmitter (Tx) and a receiver (Rx) for transmitting signals to multipoint. The 5-mm-long prototype interconnect with six transceivers performs 8 Gbps signaling with power dissipation of 1.2 mW per transceiver in a 90 nm Si CMOS process. Our interconnect achieves multipoint communications with small delay and high power efficiencies.
Date of Publication: April 2008