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Time-Domain Modeling of an RF All-Digital PLL

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3 Author(s)
Syllaios, I.L. ; Center for Integrated Circuits & Syst., Univ. of Texas at Dallas, Richardson, TX ; Staszewski, R.B. ; Balsara, P.T.

A new phase-domain all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. In this brief, we propose time-domain modeling and simulation techniques of the ADPLL that are well suited for system analysis using high-level programming languages, e.g., Matlab. They are based on the event-driven principles inherent in hardware description languages, e.g., VHDL, and enable the development of accurate and time-efficient behavioral models. The proposed techniques are demonstrated and validated through experimental results for a GSM standard.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:55 ,  Issue: 6 )