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Ultralow-Thermal-Budget CMOS Process Using Flash-Lamp Annealing for 45 nm Metal/High- k FETs

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11 Author(s)
Ootsuka, F. ; Semicond. Leading Edge Technol., Inc., Tsukuba ; Katakami, A. ; Shirai, K. ; Watanabe, T.
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This paper describes a fabrication process that uses flash-lamp annealing (FLA) and the characteristics of the CMOS transistors that are constructed with an ultralow-thermal- budget process tuned for 45-nm metal/high-k FETs. FLA enhances the drivability of pFETs with the solid-phase epitaxial (SPE) extension junction, but reducing the thermal budget deteriorates the poly-gate depletion and the electron mobility. Metal gate, however, prevents the depletion problem and leads to higher drain currents and better threshold-voltage (VTH) roll-offs when processed with tilted extension implantation combined with SPE + FLA than when processed with untilted extension implantation combined with spike rapid thermal annealing. Reducing the thermal budget is also effective in obtaining low VTH values in p-metal/HfSiON gate because of the reduced vacancy formation. Moreover, cluster-boron implantation for pFETs has superiority over monomer-boron implantation with Ge postamorphous implantation in terms of VTH roll-offs and Ion-Ioff's if FLA is used as activation. The superior electrical characteristics of full-metal- gate HfSiON transistors whose gate length is less than 50 nm, which are fabricated by using the FLA process, are demonstrated.

Published in:

Electron Devices, IEEE Transactions on  (Volume:55 ,  Issue: 4 )

Date of Publication:

April 2008

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