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The authors present two polynomial time-complexity heuristic algorithms for optimisation of gate- oxide leakage (tunnelling current) during behavioural synthesis through simultaneous scheduling and binding. One algorithm considers the time-constraint explicitly and the other considers it implicitly, whereas both account for resource constraints. The algorithms selectively bind the off-critical operations to instances of the pre-characterised resources consisting of transistors of higher oxide thickness, and critical operations to the resources of lower oxide thickness for power and performance optimisation. We design and characterise functional and storage units of different gate-oxide thicknesses and built a data path library. Extensive experiments for several behavioural synthesis benchmarks for 45 nm complementary metal-oxide- semiconductor technology showed that reduction as high as 85% can be obtained.