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A 25–75 GHz Miniature Double Balanced Frequency Doubler in 0.18- \mu m CMOS Technology

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2 Author(s)
Tsung-Yu Yang ; Nat. Central Univ., Jhongli ; Hwann-Kaeo Chiou

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm2. To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:18 ,  Issue: 4 )