Referenced Items are not available for this document.
In this paper, we suggest a topology design optimization of the address/command signals for DDR2 memory module to minimize the overshoot in waveforms when the 0.9V VTT terminations are removed for power saving and cost reduction. Simulations in frequency domain and time domain are performed for optimal signal integrity, and the optimized designs are verified by measurements.
Published in:
Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th
Date of Conference: 10-12 Dec. 2007
- Page(s):
- 922 - 925
- E-ISBN :
- 978-1-4244-1323-2
- Print ISBN:
- 978-1-4244-1323-2
- INSPEC Accession Number:
- 9863370
- Conference Location :
- Singapore
- Digital Object Identifier :
- 10.1109/EPTC.2007.4469801
- Product Type:
- Conference Publications
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