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Accurate modeling of high speed RLC interconnects has become a necessity to address signal integrity issues in current VLSI design. To accurately model a dispersive system of interconnects at higher frequencies; a full-wave analysis is required. However, conventional circuit simulation of interconnects with full-wave models is extremely CPU expensive. This paper presents an efficient full-wave analysis of RLC interconnects using frequency shift technique. Experiments have been carried out using Cadence Design Simulator which indicate that the proposed technique achieves more accuracy with less CPU time than the other model order reduction techniques existing in literature.