By Topic

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18- \mu m CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Cihun-Siyong Alex Gong ; Dept. of Electr. Eng., Nat. Central Univ., Chungli ; Muh-Tian Shiue ; Ci-Tong Hong ; Kai-Wen Yao

This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required so that considerable improvements in area and power overheads can be achieved. Moreover, its throughput becomes twice as high as that of QSERL when their frequencies of power clocks (PCs) are identical. Results on the impact of variation on CEPAL are provided. Comparison between CEPAL and other known low-power logic style achieving iso-performance, namely, subthreshold logic is also given. In order to demonstrate workability of the newly developed circuit, an 8-bit shift register, designed in the proposed techniques, has been fabricated in a TSMC 0.18-mum CMOS process. Both simulation and measurement results verify the functionality of such a logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:55 ,  Issue: 9 )