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Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder

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2 Author(s)
Xiyu Zhou ; Zhejiang Univ., Hangzhou ; Zhaoyang Zhang

This paper presents a flexible decoder architecture which supports twelve combinations of code lengths-576, 1152, 1728, 2304 bits and code rates-1/2, 2/3, 3/4 for block-serial irregular LDPC codes based on the IEEE 802.16e standard [1]. Approximate-Min Scheme is used to increase memory efficiency during message processing. At least 68.4% extrinsic message memory is saved and this reduction increases with the code rate. A prototype of the LDPC decoder has been implemented and tested on an Ateral FPGA.

Published in:

Communications and Networking in China, 2007. CHINACOM '07. Second International Conference on

Date of Conference:

22-24 Aug. 2007