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A Third-Order 9-Bit 10-MHz CMOS \Delta \Sigma Modulator With One Active Stage

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3 Author(s)
Yousry, R. ; Ain Shams Univ., Cairo ; Hegazi, E. ; Ragai, H.F.

We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-mum CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:55 ,  Issue: 9 )

Date of Publication:

Oct. 2008

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