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This paper presents a charge pump-phase locked loop (CP-PLL) that utilizes a frequency-modulated analog-to-digital converter (FM-ADC) as part of a calibration circuit to compensate for process variations and intemperate operating environments. The calibration circuitry first detects the shift in operating conditions, and then dynamically adjusts the loop bandwidth back to its nominal range to guarantee phase lock for all four process corners and the typical case, and across the telecommunications temperature range of 0 to 80 degC. Calibration comes at the expense of a worst case increase in lock time of 15% and increase of close-in phase noise of 13% for the PLL architecture examined. This self-calibrating PLL, including the FM-ADC, are designed and laid out in TSMC's 0.18-mum RF CMOS process (TSMC18RF).