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A 16-bit 65-MS/s switched-capacitors pipeline analog-to-digital converter built in 0.45-mum 25-GHz fT complementary silicon-on-insulator BiCMOS delivers 80.1-dBFS signal-to-noise ratio, 98-dBc spurious-free dynamic range (SFDR) with 3-Vpp input range at 2-MHz input frequency. The 5 times 5.3 mm2 die consumes 1.7 W from a dual plusmn2.7-V supply. A noniterative analog auto-calibration algorithm simultaneously compensates for both random mismatch in the capacitors of the first quantizer stages, and integral nonlinearity curvatures contributed by sample-and-hold (S/H) and voltage reference buffers, yielding SFDR optimizations up to 12 dB. The test chip performance validates the transient noise simulations run for the analog front-end and the clock jitter, corroborating the efficacy of the circuit techniques adopted to design S/H, clock and references.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:55 , Issue: 8 )
Date of Publication: Sept. 2008