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Towards an Integration of Low-Level Timing Analysis and Model-Based Code Generation

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6 Author(s)
Ferdinand, C. ; Abslnt Angewandte Informatik GmbH, Saarbrucken ; Heckmann, R. ; Wolff, H.-J. ; Renz, C.
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Software developers in the automotive sector must achieve high quality objectives. Many design and implementation errors are avoided by synthesizing code from model-based software specifications using automatic code generators such as ETAS' ASCET. To verify non-functional properties of the implementation, model-based design processes should be complemented with static program analysis tools like Abslnt's StackAnalyzer and timing analyzer aiT. ASCET, StackAnalyzer and aiT can be integrated in a way that the analysis results for code generated by ASCET are conveniently accessible from within the ASCET development environment. This gives ASCET users a direct feedback on the effects of their design decisions on resource usage, allowing to select more efficient designs and implementation methods. In the paper, we present the tools, the experimental integration, preliminary results and plans for further tool integration.

Published in:

Leveraging Applications of Formal Methods, Verification and Validation, 2006. ISoLA 2006. Second International Symposium on

Date of Conference:

15-19 Nov. 2006