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We present our system-level design approach adopted to improve throughput of the CWUSB MAC controller with reduced MIPS. The system-level model provides us with valuable guidance in our architecture enhancement effort and its orders of magnitude faster simulation speed allows us to use a full-fledged firmware to verify the design. Using the system-level model, we can upgrade firmware much earlier than the FPGA platform is ready and optimize the firmware using its rich set of profiling capabilities. With both architecture enhancement and firmware optimizations, we meet the bus turn-around timing requirement for CWUSB specification without using TCM or caches for most of the cases.