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This paper presents a low power, high resolution 2.4 GHz CMOS frequency synthesizer for low power wireless LAN applications. The PLL frequency synthesizer consists of a fully programmable frequency divider with a resolution of 1 MHz in the range of 2.4 GHz-2.484 GHz.The measured results showed that the programmable divider consumes 946 uA and Quadrature VCO consumes 1.57 mA and produces output swing of 650-700 mVpp. The complete synthesizer is designed using the Chartered RF 0.18 um process and synthesizer consumes 2.7 mA.
Published in:
Biomedical Circuits and Systems Conference, 2007. BIOCAS 2007. IEEE
Date of Conference: 27-30 Nov. 2007
- Page(s):
- 187 - 190
- E-ISBN :
- 978-1-4244-1525-0
- Print ISBN:
- 978-1-4244-1524-3
- INSPEC Accession Number:
- 9903415
- Conference Location :
- Montreal, Que.
- Digital Object Identifier :
- 10.1109/BIOCAS.2007.4463340
- Product Type:
- Conference Publications
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