Cart (Loading....) | Create Account
Close category search window
 

Architecting Efficient Interconnects for Large Caches with CACTI 6.0

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Muralimanohar, N. ; Univ. of Utah, Salt Lake City ; Balasubramonian, R. ; Jouppi, N.P.

Interconnects play an increasingly important role in determining the power and performance characteristics of modern processors. an enhanced version of the popular CACTI tool primarily focuses on interconnect design for large scalable caches. the new version can help evaluate novel interconnection networks for cache access and accurately estimate the delay, power, and area of large caches with uniform and nonuniform access times.

Published in:

Micro, IEEE  (Volume:28 ,  Issue: 1 )

Date of Publication:

Jan.-Feb. 2008

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.