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In this paper, an S-domain control model for a digitally- controlled dc-dc buck converter is presented. The model gives detailed description about the gain and the phase lag of each block in the control loop in digital implementation. There is a significant phase lag in the digital implementation compared to that of a analog counterpart. This model has been experimentally verified in a field- programmable-gate-array (FPGA) based DC-DC buck converter in the laboratory. The model is easily understandable and practically useful for a majority of power electronic engineers familiar with DC converters using traditional analog control to design a digital compensator. This model can be easily extended to other converter topologies.