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A New Concurrent Detection of Control Flow Errors Based on DCT Technique

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5 Author(s)
Hung-Chuan Lai ; Nat. Taiwan Univ. of Sci. & Technol., Taipei ; Shi-Jinn Horng ; Yong-Yuan Chen ; Pingzhi Fan
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In this paper, a program is first divided into several data computing blocks (DCBs) by the branch instruction; each DCB can then be recognized as an image. We then use the one dimension discrete cosine transform (1-D DCT) to compute each DCB to generate several signatures including 5-bits relay DCT signature (R-DCT-S) and 32-bits final DCT signature (F-DCT-S). These generated signatures are embedded into the instruction memory and then used to do the run time error checking. The watchdog should not reduce the processor performance, not increase the fault detection latency and not increase the memory overhead to store the signatures; in this paper, the processor degradation can be improved by doing the whole block error checking after the branch instruction, the fault detection latency is improved by doing the intermediate error checking at the R-type instruction, and the memory overhead is reduced by storing the R-DCT-S to the R-type instruction. The experimental results show that the proposed watchdog has very high error detection coverage and shortest error detection latency to detect either single fault or multi-faults, no matter what the fault is transient or intermittent.

Published in:

Dependable Computing, 2007. PRDC 2007. 13th Pacific Rim International Symposium on

Date of Conference:

17-19 Dec. 2007