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Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures

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3 Author(s)
Hsin-Chou Chi ; Nat. Dong Hwa Univ., Hualien ; Chia-Ming Wu ; Jun-Hui Lee

Network-on-chip (NoC) architectures provide a high-performance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput, and hence are suitable for NoC architectures with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication paths, and allocates a proper bandwidth for each communication path. Simulation results show that our design provides an effective solution for a critical step in the NoC design. The cost and latency of the switch in the circuit-switched network can be lowered down with our scheme.

Published in:

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Date of Conference:

23-25 Jan. 2008