VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher

In this paper, we propose a VLSI architecture and an FPGA implementation of a hybrid message-embedding (HME) self-synchronizing stream cipher encryption based on a switched linear congruent pseudo-random generator. This encryption, which is based on a chaotic scheme, is particularly attractive since it provides the same security as any conventional self-synchronizing stream cipher requiring only additions, subtractions, multiplications and word-switch operations. We show its feasibility and its implementation which are presented and detailed by using Altera FPGA technology for a set of parameter numbers (switching and key component number). We also show the parametrable of the HME in order to obtain the appropriate security and a the best trade off between the smallest FPGA logical area and the best throughputs rate for embedded applications.