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This paper presents a comparative study of sub-32 nm CMOS 6T SRAM cells in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar self-aligned gates. Both independent- and connected- gate operation is analysed by modulating the drain current with both front and back gate voltages. The four studied cells take advantage of their transistor back gates to improve stability while optimizing write operation. These are the two key criteria used in the presented sizing method. The results of read-, retention- and write margins and area are displayed for all cells in the presence of process variability.