By Topic

Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tao Wang ; Tsinghua Univ., Beijing ; Liping Liang

This paper presents the non-idealities analysis, modelling and circuit implementation of a second-order two-bit Continuous-Time (CT) Sigma-Delta Modulator (SDM). The non-idealities such as quantizer metastability, clock jitter, finite integrator DC gain, circuit noises and non-linearities are discussed. Discrete time (DT) SDM model is first developed and then mapped onto CT-SDM model. Finally the circuit is implemented in 130 nm CMOS technology. It achieves a simulated 53.6 dB DR and 51.4 dB SNDR over a 20MHz signal bandwidth. The sampling clock frequency is 640 MHz, producing an Over-Sampling-Ratio (OSR) of 16. Second order loop is intrinsically stable, while higher order loops tend to be unstable and much effort must be taken to maintain stability. Multi-bit internal quantizer is employed to obtain more aggressive quantization noise suppression and lower clock jitter sensitivity compared with higher order single bit structure. Spectre simulation shows that the power dissipation of the circuit is about 6 mW at 1.8 V supply.

Published in:

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Date of Conference:

23-25 Jan. 2008