By Topic

A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jie Guo ; Dresden Univ. of Technol., Dresden ; Jun Liu ; Mennenga, B. ; Fettweis, G.P.

This paper starts with the introduction of the Synchronous Transfer Architecture (STA), a new variant of VLIW architecture which can be viewed as a version of Transport-Triggered Architectures (TTA). Since the quality of assembly code generated by traditional high-level language compiler for such architectures is not satisfactory, we propose a novel phase-coupled compiler, in which the instruction selection and register allocation are solved together by using a two-step register allocator. According to our studies, this approach can reduce both execution time and size of the generated code by about 40%-60% in comparison to code assembled by conventional (phase-separated) compilers. Moreover, assembly code quality achieved by using two-step register allocation is comparable to the code quality obtained by a phase-coupled compiler backend based on Integer Linear Programming which requires much longer compilation time.

Published in:

Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on

Date of Conference:

9-11 July 2007