An Analytical Expression for Drain Saturation Voltage of Polycrystalline Silicon Thin-Film Transistors

A physical-based analytical expression for the drain saturation voltage V
_Dsat
of polycrystalline silicon (poly-Si) thin- film transistors (TFTs) is derived. V
_Dsat
is found to be dominated by the grain boundary potential barrier modulation effect, which can be readily estimated from the device transfer characteristic. Straightforward prediction of V
_Dsat
values at arbitrarily given gate voltages based on the proposed formula is demonstrated for both low temperature and high temperature processed poly-Si TFTs in either n- or p-type. The prediction agrees well with experimentally determined VDsat value. Derivation of the expression is based on our previously proposed analytical ON-state drain-current model for poly-Si TFTs, with no empirical factors included.